20th International Symposium on Computer Architecture & Digital Systems






Important Dates


Keynote Speakers

It is great pleasure to introduce the following guests as the keynote speakers for the event:

Behrooz Parhami
Professor Behrooz Parhami Electrical and Computer Engineering

Department of Electrical and Computer Engineering
University of California
Santa Barbara, CA 93106-9560, USA
Office location: Harold Frank Hall, Room 5155
Deliveries: Harold Frank Hall, Room 4155
Office phone: +1 805 893 3211
Departmental fax: +1 805 893 3262

Title: Neurophysiological Discoveries of the 2014 Nobel Prize Winners in Medicine from a Computer Arithmetic Perspective

Abstract: The discovery that mammals use a multi-modular method akin to residue number system (RNS), but with continuous residues or digits, to encode position information led to the award of the 2014 Nobel Prize in Medicine. After a brief review of the evidence in support of this hypothesis, and how it relates to RNS, I discuss the properties of continuous-digit RNS, and discuss results on the dynamic range, representational accuracy, and factors affecting the choice of the moduli, which are themselves real numbers. I conclude with suggestions for further research on important open problems concerning the process of selection, or evolutionary refinement, of the set of moduli in such a representation.

Kenneth B. Kent
Professor Kenneth B. Kent Ph.D., M.Sc. (University of Victoria); B.Sc. (Memorial University of Newfoundland) Faculty of Computer Science University of New Brunswick

Dr. Kenneth B. Kent, P. Eng.
Professor & Director, IBM Centre for Advanced Studies - Atlantic
Faculty of Computer Science, University of New Brunswick
540 Windsor Street, Fredericton, New Brunswick, E3B 5A3
ph. (506) 451-6971
fax. (506) 453-3566
Honorary Professor, Department of Computer Science and Institute of Visual Computing
Bonn-Rhein-Sieg University of Applied Sciences
Grantham-Allee 20, 53757 Sankt Augustin, Germany

Title:Verilog-to-Routing: High Performance CAD and Customizable FPGA Architecture Modelling

Abstract: In the face of both emerging and legacy application domains, and changes to manufacturing process technology, it is challenging to develop new Field Programmable Gate Array (FPGA) architectures. This is due in part to the difficulty of fairly evaluating FPGA architectural choices, which requires sophisticated Computer Aided Design (CAD) tools to target potential architectures. My talk will present version 8.0 of the open source Verilog-to-Routing (VTR) project, which provides such a design flow and can target a variety of FPGA architectures. In VTR 8 we have expanded the scope of FPGA architectures that can be modelled, giving FPGA architects more flexibility to customize their architectures, and enhanced the CAD flow for better interoperability with other tools. Together these enhancements allow VTR to target and model many details of both commercial and proposed FPGA architectures. The VTR design flow also serves as a baseline for evaluating new CAD algorithms. It is therefore important, for both the validity of architectural conclusions and CAD algorithm comparisons, that VTR produce high-quality circuit implementations. In addition to presenting some of the new features of VTR 8.0, I will discuss some of the on-going research that we are performing on circuit optimization in the context of hard blocks and the trade-offs associated between speed and size when performing high-level synthesis.

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Latest news about CADS 2020 in Guilan University


"Due to the COVID-19 pandemic, we are tentatively postponing the proceedings of CADS 2020 to be held on August 19 and 20, 2020.

Based on the circumstances and new decisions by the University officials, we may have to arrange recorded or live remote presentations, which will be duly announced."


"Due to the spread of the Corona virus, the deadline for submitting manuscripts has been extended to the end of March 2020"

"Notification for accepted papers will be announced as soon as the reviewer’s comments are received."

new conference dates

"Due to the conditions caused by the Corona Virus, specially in Guilan, we cannot host the conference on the announced dates. Please be advised that the new conference dates sometime in June 2020. The exact dates will be announced later. Therefore, the manuscript submission date is extended at least until the end of March."

Selected papers

Selected papers will be nominated for extension in order to be considered for publication in The CSI journal on Computer Science and Engineering OR AUT Journal of Electrical Engineering.

Special Issue in AUT Journal of Electrical Engineering:

Selected papers will be nominated for extension in order to be considered for publication in AUT Journal of Electrical Engineering , November 20, 2019.

Keynote speaker #2 approved:

Prof. Kenneth B. Kent, January 8, 2020.

Keynote speaker #1 approved:

Prof. Behrooz Parhami, January 5, 2020.